1. Field of the Invention
The present invention generally relates to obtaining a layout design of an existing integrated circuit, and, more particularly, to obtaining a layout design of an existing integrated circuit comprising an array of repeating unit structures.
2. Description of the Prior Art
In the semiconductor industry, it is usually desired to be able to inspect an existing integrated circuit (IC) for obtaining design and/or layout information thereof. The inspection may be useful for, for example, correcting errors in circuit design, functionality, layout connectivity, etc for fabricating a semiconductor circuit, especially a large-scale one, or, for example, reverse engineering an existing IC to extract layout or design information. For the inspection, referring to FIG. 1, for example, the die including the IC is deconstructed by a sequence of layer-removal processes, to reveal components 4a, 4b, 4c in various layers 6, 8, 10 step-by-step. The layer-removal processes may be for example a sequence of etching steps to reveal a single element in, such as an interconnecting metal layer, a polycrystalline silicon layer, an oxide layer, a silicide layer, etc., and/or a sequence of polishing steps to reveal components on each polished surface.
However, in addition to time consuming for both etching and polishing procedure for revealing the IC layout structure layer by layer, some components or elements may be not seen due to being covered by others, and when the structure is polished step-by-step, elements revealed in a single polished surface do not provide sufficient information about vertical spatial relations of each other. For example, when word lines or bit lines are revealed on one surface, capacitors are not be seen, and little clues are shown for the relative position between the word lines and the capacitor or between the bit lines and the capacitors. These are disadvantages for analyzing the exact structure. Furthermore, certain components or elements in the IC may tend to be etched off or polished off in one single step of removal without awareness so as to result in an erroneous layout structure.
Therefore, there is still a need for a novel method for obtaining a layout design of an existing integrated circuit fast, efficiently and accurately.